Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG 2000: Image Compression Fundamentals, Standards and Practice
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
High-performance arithmetic coding VLSI macro for the H264 video compression standard
IEEE Transactions on Consumer Electronics
A high performance CABAC decoding architecture
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance architecture for embedded block coding in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
High-Throughput Architecture for H.264/AVC CABAC Compression System
IEEE Transactions on Circuits and Systems for Video Technology
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
Journal of Signal Processing Systems
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This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm2 when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.