A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC
Journal of Signal Processing Systems
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
An FPGA architecture for CABAC decoding in manycore systems
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
High-throughput H.264/AVC high-profile CABAC decoder for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high performance CABAC decoding architecture
IEEE Transactions on Consumer Electronics
A high-performance hardwired CABAC decoder for ultra-high resolution video
IEEE Transactions on Consumer Electronics
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
High-Speed H.264/AVC CABAC Decoding
IEEE Transactions on Circuits and Systems for Video Technology
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Video encoding and decoding are computing intensive applications that require high performance processors or dedicated hardware. Video decoding offers a high parallel processing potential that may be exploited. However, a particular task challenges parallelization: entropy decoding. In H.264 and SVC video standards, this task is mainly carried out using arithmetic decoding, an strictly sequential algorithm that achieves results close to the entropy limit. By accelerating arithmetic decoding, the bottleneck is removed and parallel decoding is enabled. Many works have been published on accelerating pure binary encoding and decoding. However, little research has been done into how to integrate binary decoding with context managing and control without losing performance. In this work we propose a FPGA-based architecture that achieves real time decoding for high-definition video by sustaining a 1 bin per cycle throughput. This is accomplished by implementing fast bin decoding; a novel and area efficient context-managing mechanism; and optimized control scheduling.