A high performance CABAC decoding architecture

Authors:
Wei Yu;Yun He
Affiliations:
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
2005

Citing 0
Cited 10

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Survey of Advanced CABAC Accelerator Architectures for Future Multimedia

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CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

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High-throughput H.264/AVC high-profile CABAC decoder for HDTV applications

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Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding

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ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
A novel pipeline design for H.264 CABAC decoding

PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
A high throughput CABAC algorithm using syntax element partitioning

ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard

Journal of Signal Processing Systems

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Abstract

In this paper, we propose a high performance hardware architecture of CABAC decoder CABAC is the context adaptive binary arithmetic coding used in H.264/AVC video standard, which achieves significant compression enhancement while bringing greater complexity and costs in implementation. The necessity of hardware implementation for real-time CABAC decoders is introduced, and then a fast and cost effective architecture is proposed. The new architecture can achieve decoding speed of averagely 500 cycles/macroblock, for typical 4M bit stream of DI resolution, 30 frame/s. An ASIC implementation of the new architecture is carried out in a 0.18 μm silicon technology. The estimated area is 0.3 mm2 and the critical path is limited within 6.7 ns.