ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC
Journal of Signal Processing Systems
Proceedings of the 21st annual symposium on Integrated circuits and system design
Implementation Strategies for Statistical Codec Designs in H.264/AVC Standard
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
An FPGA architecture for CABAC decoding in manycore systems
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
A novel pipeline design for H.264 CABAC decoding
PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
Accelerating CABAC encoding for multi-standard media with configurability
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A high performance CABAC decoding architecture
IEEE Transactions on Consumer Electronics
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
High-Throughput Architecture for H.264/AVC CABAC Compression System
IEEE Transactions on Circuits and Systems for Video Technology
High-Speed H.264/AVC CABAC Decoding
IEEE Transactions on Circuits and Systems for Video Technology
A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC
IEEE Transactions on Circuits and Systems for Video Technology
Design of massively parallel hardware multi-processors for highly-demanding embedded applications
Microprocessors & Microsystems
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The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems require efficient video coding algorithms and corresponding adaptive high-performance computational platforms. The H.264/AVC video coding algorithms provide high enough compression efficiency to be utilized in these systems, and multimedia processors are able to provide the required adaptability, but the algorithms complexity demands for more efficient computing platforms. Heterogeneous (re-)configurable systems composed of multimedia processors and hardware accelerators constitute the main part of such platforms. In this paper, we survey the hardware accelerator architectures for Context-based Adaptive Binary Arithmetic Coding (CABAC) of Main and High profiles of H.264/AVC. The purpose of the survey is to deliver a critical insight in the proposed solutions, and this way facilitate further research on accelerator architectures, architecture development methods and supporting EDA tools. The architectures are analyzed, classified and compared based on the core hardware acceleration concepts, algorithmic characteristics, video resolution support and performance parameters, and some promising design directions are discussed. The comparative analysis shows that the parallel pipeline accelerator architecture seems to be the most promising.