On high-bandwidth data cache design for multi-issue processors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Evaluating MMX technology using DSP and multimedia applications
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Computer Architecture: Concepts and Evolution
Computer Architecture: Concepts and Evolution
IEEE Transactions on Computers
Implementation and Evaluation of the Complex Streamed Instruction Set
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
An Architectural Overview of the Programmable Multimedia Processor, TM-1
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
The Reconfigurable Streaming Vector Processor (RSVPTM)
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Motion estimation performance of the TM3270 processor
Proceedings of the 2005 ACM symposium on Applied computing
Instruction Set Architecture Enhancements for Video Processing
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
The Equator MAP-CA™ DSP: an end-to-end broadband signal processor™ VLIW
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
Avoiding conversion and rearrangement overhead in SIMD architectures
International Journal of Parallel Programming
Inter-cluster communication in VLIW architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Configurable data memory for multimedia processing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
VLSI architecture design approaches for real-time video processing
WSEAS Transactions on Circuits and Systems
Parallel H.264 Decoding on an Embedded Multicore Processor
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
An Enhanced DMA Controller in SIMD Processors for Video Applications
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
EMPIRE: Empirical power/area/timing models for register files
Microprocessors & Microsystems
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Extending an embedded RISC microprocessor for efficient translation based Java execution
Microprocessors & Microsystems
IEEE Transactions on Circuits and Systems for Video Technology
Improving TriMedia cache performance by profile guided code reordering
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Scalable stochastic processors
Proceedings of the Conference on Design, Automation and Test in Europe
A multithreaded multicore system for embedded media processing
Transactions on high-performance embedded architectures and compilers III
A highly scalable parallel implementation of h.264
Transactions on High-Performance Embedded Architectures and Compilers IV
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Scheduling for register file energy minimization in explicit datapath architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Shared-port register file architecture for low-energy VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
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We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing, combined with embedded processor requirements for the consumer market. We discuss the architecture, implementation, and its first realization in a 90 nm process technology. The processor incorporates instruction set architectural (ISA) extensions and a load/store unit optimized for the video-processing domain. The ISA extensions improve the performance on video processing kernels. The data cache policies and prefetching techniques allow for efficient access to multimedia data. Finally, power consumption and performance data are presented.