On high-bandwidth data cache design for multi-issue processors

  • Authors:

  • Jude A. Rivers;Gary S. Tyson;Edward S. Davidson;Todd M. Austin

  • Affiliations:

  • Advanced Computer Architecture Laboratory, The University of Michigan;Advanced Computer Architecture Laboratory, The University of Michigan;Advanced Computer Architecture Laboratory, The University of Michigan;Microcomputer Research Labs, Intel Corporation

  • Venue:
  • MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1997

Quantified Score

Hi-index 0.00

Visualization

Abstract

Highly aggressive multi-issue processor designs of the past few years and projections for the decade, require that we redesign the operation of the cache memory system. The number of instructions that must be processed (including incorrectly predicted ones) will approach 16 or more per cycle. Since memory operations account for about a third of all instructions executed, these systems will have to support multiple data references per cycle. In this paper, we explore reference stream characteristics to determine how best to meet the need for ever increasing access rates. We identify limitations of existing multi-ported cache designs and propose a new structure, the Locally-Based Interleaved Cache (LBIC), to exploit the characteristics of the data reference stream while approaching the economy of traditional multi-bank cache design. Experimental results show that the LBIC structure is capable of outper forming current multi-ported approaches.