Performance evaluation of vector accesses in parallel memories using a skewed storage scheme
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A close look at vector performance of register-to-register vector computers and a new model
SIGMETRICS '87 Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
An Analysis of Vector Startup Access Delays
IEEE Transactions on Computers
Performance evaluation of static and dynamic memory systems on the Cray-2
ICS '88 Proceedings of the 2nd international conference on Supercomputing
A dynamic storage scheme for conflict-free vector access
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Perfect Latin squares and parallel array access
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Analysis of vector access performance on skewed interleaved memory
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The impact of memory organization on the performance of matrix multiplication
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
On randomly interleaved memories
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Conflict-Free Vector Access Using a Dynamic Storage Scheme
IEEE Transactions on Computers
Reducing memory contention in shared memory multiprocessors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
A ultra fast Euclidean division algorithm for prime memory systems
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
IEEE Transactions on Computers
A novel cache design for vector processing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Increasing the number of strides for conflict-free vector access
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Conflict-free access of vectors with power-of-two strides
ICS '92 Proceedings of the 6th international conference on Supercomputing
Memory contention for shared memory vector multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Introducing a New Cache Design into Vector Computers
IEEE Transactions on Computers
Synchronized access to streams in SIMD vector multiprocessors
ICS '94 Proceedings of the 8th international conference on Supercomputing
On Memory Contention Problems in Vector Multiprocessors
IEEE Transactions on Computers
A Memory Interference Model for Regularly Patterned Multiple Stream Vector Accesses
IEEE Transactions on Parallel and Distributed Systems
Accounting for memory bank contention and delay in high-bandwidth multiprocessors
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Vector multiprocessors with arbitrated memory access
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Reducing inter-vector-conflicts in complex memory systems
ICS '96 Proceedings of the 10th international conference on Supercomputing
OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses
ICS '90 Proceedings of the 4th international conference on Supercomputing
Data caches for superscalar processors
ICS '97 Proceedings of the 11th international conference on Supercomputing
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
On high-bandwidth data cache design for multi-issue processors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems
IEEE Transactions on Computers
Co-design of interleaved memory systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Increasing the effective bandwidth of complex memory systems in multivector processors
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
IEEE Transactions on Computers
Reducing Interference Among Vector Accesses in Interleaved Memories
IEEE Transactions on Computers
Analytical Estimation of Vector Access Performance in Parallel Memory Architectures
IEEE Transactions on Computers
Conflict-Free Access for Streams in Multimodule Memories
IEEE Transactions on Computers
Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
IEEE Transactions on Parallel and Distributed Systems
Symbolic Performance Modeling of Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
Memory access reordering in vector processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Multiaccess Memory System for Attached SIMD Computer
IEEE Transactions on Computers
WBTK: a New Set of Microbenchmarks to Explore Memory System Performance for Scientific Computing
International Journal of High Performance Computing Applications
The design space of data-parallel memory systems
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A One's Complement Cache Memory
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit
Journal of Signal Processing Systems
The impact of memory organization on the performance of matrix calculations
Parallel Computing
Practical aspects and experiences: CRAY X-MP and Y-MP memory performance
Parallel Computing
SAMS multi-layout memory: providing multiple views of data to boost SIMD performance
Proceedings of the 24th ACM International Conference on Supercomputing
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