On the effective bandwidth of interleaved memories in vector processor systems
IEEE Transactions on Computers
An Efficient Memory System for Image Processing
IEEE Transactions on Computers
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
On Linear Skewing Schemes and d-Ordered Vectors
IEEE Transactions on Computers
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Scrambled storage for parallel memory systems
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Perfect Latin squares and parallel array access
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
On randomly interleaved memories
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Conflict-Free Vector Access Using a Dynamic Storage Scheme
IEEE Transactions on Computers
IEEE Transactions on Computers
An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid
IEEE Transactions on Parallel and Distributed Systems
An Efficient Buffer Memory System for Subarray Access
IEEE Transactions on Parallel and Distributed Systems
A Multiaccess Frame Buffer Architecture
IEEE Transactions on Computers
Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
IEEE Transactions on Parallel and Distributed Systems
Multiskewing-A Novel Technique for Optimal Parallel Memory Access
IEEE Transactions on Parallel and Distributed Systems
HMESH: A VLSI Architecture for Parallel Processing
CONPAR '86 Conference on Algorithms and Hardware for Parallel Processing
Survey of Commercial Parallel Machines
Survey of Commercial Parallel Machines
An optimized linear skewing interleave scheme for on-chip multi-access memory systems
Proceedings of the 17th ACM Great Lakes symposium on VLSI
High-bandwidth Address Generation Unit
Journal of Signal Processing Systems
| Hi-index | 14.98 |
In order to reduce the memory access time for a Single-Instruction Multiple-Data stream (SIMD) computer with pq processing elements attached to a host computer, a multiaccess memory system is proposed in this paper. The proposed memory system supports simultaneous access to pq data elements within a 4-directional block (p 脳 q), a row (1 脳 pq), a column (pq 脳 1), a forward-diagonal, and a backward-diagonal subarray with a constant interval in an arbitrary position in an M脳N array of data elements, where the number of memory modules, m, is a prime number greater than pq. For the simple and fast address calculation and routing circuit, the address differences between the pq addresses and the base address are arranged in ascending order according to the index numbers of m memory modules from the index number of memory module of the first element. The proposed multiaccess memory system provides more subarray types and more constant intervals than the previous memory systems.