Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
An Efficient Memory System for Image Processing
IEEE Transactions on Computers
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Conflict-free access of arrays in a parallel processor
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Perfect Latin squares and parallel array access
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
An aperiodic storage scheme to reduce memory conflicts in vector processors
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
On randomly interleaved memories
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
IEEE Transactions on Computers
Architecture of an Array Processor Using a Nonlinear Skewing Scheme
IEEE Transactions on Computers
Semi-linear and bi-base storage schemes classes: general overview and case study
ICS '95 Proceedings of the 9th international conference on Supercomputing
A Multiaccess Frame Buffer Architecture
IEEE Transactions on Computers
Buffered Banks in Multiprocessor Systems
IEEE Transactions on Computers
Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
IEEE Transactions on Parallel and Distributed Systems
Latin Squares for Parallel Array Access
IEEE Transactions on Parallel and Distributed Systems
Memory access reordering in vector processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Multiaccess Memory System for Attached SIMD Computer
IEEE Transactions on Computers
Array organization in parallel memories
International Journal of Parallel Programming
A performance study of buffered pseudorandomly interleaved memories with multiple sections
Mathematical and Computer Modelling: An International Journal
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A scrambled storage scheme is proposed for storing arrays of NXN elements in N = 2n parallel memory modules to allow conflict-free access to various array partitions. It is shown that the scheme allows conflict-free access to rows, columns, square blocks, and distributed blocks of stored arrays. An alternative way of achieving the desired accessibility would use Budnik and Kuck's nonuniform skewed storage [3]; in this case, addressing hardware would require &Ogr;(nX2n) exclusive-or circuits. The proposed scheme has, however, the advantage of simplifying address generation; addressing hardware requires n exclusive-or circuits only. Some of the important questions of scrambling/unscrambling data through a proposed interconnection network are discussed.