An aperiodic storage scheme to reduce memory conflicts in vector processors

Authors:
S. Weiss
Affiliations:
Department of Computer Science, University of Maryland - BC, Baltimore, MD and Institute for Advanced Computer Studies, University of Maryland - CP, College Park, MD
Venue:
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Year:
1989

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Abstract

One of the most noticeable differences between the CRAY-2 and its predecessors, the CRAY-1 and the CRAY X-MP, is a significantly longer memory path. This is a consequence of increasing the size of the memory at the expense of the bank access time. With a longer memory path, the impact of bank conflicts becomes more apparent. In this paper we study a storage strategy for vector processors that has the following properties: (1) it is aperiodic, (2) it tends to distribute references more uniformly over the memory banks, (3) the implementation of the addressing hardware is straightforward, and (4) the delay added to the memory path is minimal. The first two properties help in reducing the frequency of bank conflicts.