Derivation of a Waiting-Time Factor for a Multiple-Bank Memory
Journal of the ACM (JACM)
Multiprocessor memory organization and memory interference
Communications of the ACM
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Anaysis of interleaved memory systems using blockage buffers
Communications of the ACM
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Program Behavior and the Performance of Interleaved Memories
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Activity in an Interleaved Memory
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
On the Bandwidth and Interference in Interleaved Memory Systems
IEEE Transactions on Computers
Optimul: An optional interconnect for multiprocessor systems
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Performance evaluation of static and dynamic memory systems on the Cray-2
ICS '88 Proceedings of the 2nd international conference on Supercomputing
An aperiodic storage scheme to reduce memory conflicts in vector processors
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Analysis of vector access performance on skewed interleaved memory
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Behavioral characterization of multiprocessor memory systems: a case study
SIGMETRICS '89 Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Some results in memory conflict analysis
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Experimentally Characterizing the Behavior of Multiprocessor Memory Systems: A Case Study
IEEE Transactions on Software Engineering
Architecture and implementation of a VLIW supercomputer
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Data prefetching in multiprocessor vector cache memories
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Performance results for two of the NAS parallel benchmarks
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
IEEE Transactions on Computers
A novel cache design for vector processing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Characterizing memory performance in vector multiprocessors
ICS '92 Proceedings of the 6th international conference on Supercomputing
Memory contention for shared memory vector multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
A case for Wafer-scale interconnected memory arrays
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Introducing a New Cache Design into Vector Computers
IEEE Transactions on Computers
Synchronized access to streams in SIMD vector multiprocessors
ICS '94 Proceedings of the 8th international conference on Supercomputing
On Memory Contention Problems in Vector Multiprocessors
IEEE Transactions on Computers
A Memory Interference Model for Regularly Patterned Multiple Stream Vector Accesses
IEEE Transactions on Parallel and Distributed Systems
Accounting for memory bank contention and delay in high-bandwidth multiprocessors
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Vector multiprocessors with arbitrated memory access
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Matrix Partitioning on a Virtual Shared Memory Parallel Machine
IEEE Transactions on Parallel and Distributed Systems
Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems
IEEE Transactions on Computers
Access conflicts in multiprocessor memories queueing models and simulation studies
ICS '90 Proceedings of the 4th international conference on Supercomputing
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A Comparative Analysis of Cache Designs for Vector Processing
IEEE Transactions on Computers
High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
IEEE Transactions on Computers
Buffered Banks in Multiprocessor Systems
IEEE Transactions on Computers
Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
IEEE Transactions on Parallel and Distributed Systems
Models of Access Delays in Multiprocessor Memories
IEEE Transactions on Parallel and Distributed Systems
Memory access reordering in vector processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Multiaccess Memory System for Attached SIMD Computer
IEEE Transactions on Computers
Efficient gather and scatter operations on graphics processors
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Sams: single-affiliation multiple-stride parallel memory scheme
Proceedings of the 2008 workshop on Memory access on future processors: a solved problem?
Unfavorable Strides in Cache Memory Systems (RNR Technical Report RNR-92-015)
Scientific Programming
High-bandwidth Address Generation Unit
Journal of Signal Processing Systems
A performance study of buffered pseudorandomly interleaved memories with multiple sections
Mathematical and Computer Modelling: An International Journal
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A number of recent vector supercomputer designs have featured main memories with very large capacities, and presumably even larger memories are planned for future generations. While the memory chips used in these computers can store much larger amounts of data than before, their operation speeds are rather slow when compared to the significantly faster CPU (central processing unit) circuitry in new supercomputer designs. A consequence of this speed disparity between CPU's and main memory is that memory access times and memory bank reservation times (as measured in CPU ticks) are sharply increased from previous generations.