Performance Analysis of Cache Memories
Journal of the ACM (JACM)
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Cache memories for PDP-11 family computers
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Performance evaluation and prediction of storage hierarchies
PERFORMANCE '80 Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation
An instruction timing model of CPU performance
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Computer
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Cache system design in the tightly coupled multiprocessor system
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
On the Bandwidth and Interference in Interleaved Memory Systems
IEEE Transactions on Computers
Effects of storage contention on system performance
IBM Systems Journal
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Abstracting network characteristics and locality properties of parallel systems
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Performance analysis of future shared storage systems
IBM Journal of Research and Development
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This paper presents an approximate analytical model for the performance of multiprocessors with private cache memories and a single shared main memory. The accuracy of the model is compared with simulation results and is found to be very good over a broad range of parameters. The parameters of the model are the size of the multiprocessor, the size and type of the interconnection network, the cache miss-ratio, and the cache block transfer time. The analysis is extended to include several different read/write policies such as write-through, load-through, and buffered write-back. The analytical technique presented is also applicable to the performance of interconnection networks under block transfer mode.