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Analytic models for memory interference in multiprocessor computer systems.
Analytic models for memory interference in multiprocessor computer systems.
Computer structures: Readings and examples (McGraw-Hill computer science series)
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Exact performance estimates for multiprocessor memory and bus interference
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Vector Computer Memory Bank Contention
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IEEE Transactions on Computers
Performance analysis of the FFT algorithm on a shared-memory parallel architecture
IBM Journal of Research and Development
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Effects of buffered memory requests in multiprocessor systems
SIGMETRICS '79 Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, measurement and modeling of computer systems
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IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
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Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
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IEEE Transactions on Computers
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Multiple-Read Single-Write Memory and Its Applications
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
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IEEE Transactions on Computers
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IEEE Transactions on Computers
Architecture Optimization of Aerospace Computing Systems
IEEE Transactions on Computers
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IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
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IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
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Cache system design in the tightly coupled multiprocessor system
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IBM Journal of Research and Development
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IEEE Transactions on Computers - Special issue on parallel processors and processing
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Journal of Systems and Software
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This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.