ACM Transactions on Computer Systems (TOCS)
A Generalized Timed Petri Net Model for Performance Analysis
IEEE Transactions on Software Engineering
Analyzing queueing networks with simultaneous resource possession
Communications of the ACM
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
A Generalized Timed Petri Net Model for Performance Analysis
International Workshop on Timed Petri Nets
Extended Stochastic Petri Nets: Applications and Analysis
Performance '84 Proceedings of the Tenth International Symposium on Computer Performance Modelling, Measurement and Evaluation
An approximate analysis of multiprocessor systems
SIGMETRICS '83 Proceedings of the 1983 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Timed Petri nets and preliminary performance evaluation
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Markov chain models for analyzing memory interference in multiprocessor computer systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
On the integration of delay and throughput measures in distributed processing models
On the integration of delay and throughput measures in distributed processing models
Modeling Bus Contention and Memory Interference in a Multiprocessor System
IEEE Transactions on Computers
Interference in Multiprocessor Systems with Localized Memory Access Probabilities
IEEE Transactions on Computers
An Analysis of Processor-Memory Interconnection Networks
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Program Behavior and the Performance of Interleaved Memories
IEEE Transactions on Computers
Performance of Cross-Bar Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System
IEEE Transactions on Computers
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Performance analysis of future shared storage systems
IBM Journal of Research and Development
C2MP: a cache-coherent, distributed memory multiprocessor-system
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
On the execution of parallel programs on multiprocessor systems—a queuing theory approach
Journal of the ACM (JACM)
Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets
IEEE Transactions on Computers
Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
Performance Model for a Prioritized Multiple-Bus Multiprocessor System
IEEE Transactions on Computers
A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
An Easy-to-Use Approach for Practical Bus-Based System Design
IEEE Transactions on Computers
The GTPN analyzer: numerical methods and user interface
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Performance Modeling and Evaluation of Circuit Switching Using Clos Networks
IEEE Transactions on Computers
Locking Performance in a Shared Nothing Parallel Database Machine
IEEE Transactions on Knowledge and Data Engineering
A Multiprocessor Bus Design Model Validated by System Measurement
IEEE Transactions on Parallel and Distributed Systems
A Comprehensive Performance Evaluation of Crossbar Networks
IEEE Transactions on Parallel and Distributed Systems
Timed Petri net models of multithreaded multiprocessor architectures
PNPM '97 Proceedings of the 6th International Workshop on Petri Nets and Performance Models
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Exact results are given for the processing power in a multibus multiprocessor with constant memory cycle times and geometric interrequest times. Both uniform and nonuniform memory accesses are considered. Such results have not previously been obtained. In order to derive these results we use a method of introducing time into Petri nets, called Generalized Timed Petri Nets (GTPN), that we have developed. We describe the GTPN and how it is applied to the multiprocessor interference question. We reach several new conclusions. A commonly used definition of processing power can lead to substantial underestimation of the true processing power of the system. If the real system has a constant memory access time and any number of buses, then assuming an exponential access time can lead to substantial errors when estimating processing power probability distributions. In multibus systems with only a few buses a critical memory interrequest time exists. Performance close to that with a crossbar is attainable when the interrequest time is larger than the critical value. Obtaining these results illustrates the advantages, for moderate size state spaces, of the GTPN over simulation with respect to both model design and running time.