An Analysis of Processor-Memory Interconnection Networks

Authors:
L. N. Bhuyan
Affiliations:
Department of Electrical and Computer Engineering, University of Southwestern Louisiana
Venue:
IEEE Transactions on Computers
Year:
1985

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Abstract

An interference analysis of the interconnection networks (IN's) for tightly coupled multiprocessors is presented in this correspondence. The interconnections considered are crossbars and delta networks. Two situations are examined: when a memory module is equally likely to be addressed by a processor and when a processor has a favorite memory. It is shown that for a higher rate of favorite requests, the delta networks perform close to a crossbar.