Analysis of multiple-bus interconnection networks
Journal of Parallel and Distributed Computing
Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Interference in Multiprocessor Systems with Localized Memory Access Probabilities
IEEE Transactions on Computers
An Analysis of Processor-Memory Interconnection Networks
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
Effects of storage contention on system performance
IBM Systems Journal
A combinatorial approach to performance analysis of a shared-memory multiprocessor
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
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We present a discrete Markov chain model for analyzing the effect of memory interference in processor-memory interconnections of buffered multiprocessor systems. Each module is assumed to be one of the following three types-hot memory, favorite memory and memory which is neither hot nor favorite. The analytical solutions are restricted to 2/spl times/M and N/spl times/2 systems, where N and M are respectively the number of processors and memory modules. The general case is analyzed using simulation studies and compared with the analytic results. In all cases the main criterion of the system performance are the effective bandwidth, mean queue length and mean waiting time for a memory request. It is expected that increasing the number K of hot modules will improve the performance. We also estimate the asymptotic bandwidth and propose a heuristic to find an upper bound on K beyond which the bandwidth saturates.