IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Experiences with Performance Measurement and Modeling of a Processor Array
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Memory and Bus Conflict in an Array Processor
IEEE Transactions on Computers
Performance of Cross-Bar Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Multiple Microprocessors with Common Main and Control Memories
IEEE Transactions on Computers
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers
A combinatorial approach to performance analysis of a shared-memory multiprocessor
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
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This paper presents a mathematical model to measure the amount by which a computer's speed is reduced when it time-shares storage with other computers and I/O channels. The method can be applied to any number of processors and/or channels and storage units, although the complexity of the solution does increase rapidly as the number of processors increases. Explicit formulas and numerical results are given for several special cases. The results of a simulation of a shared-memory multiprocessor are presented, showing how closely the mathematical model fits the operation of a simulated system.