Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Markov chain models for analyzing memory interference in multiprocessor computer systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
Effects of storage contention on system performance
IBM Systems Journal
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
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This correspondence develops two discrete memory interference models. These models, the equivalent rate model and the Markov chain model, provide for variable connection times between processors and memories if these times can be characterized by a discrete random variable X. The equivalent rate model, which is the simpler, requires only the first moment of X, while the Markov chain model requires the first and second moments. The models yield estimates of the bandwidth BW, the probability of acceptance Pa, and processor utilization Up. Both models give good estimates of BW when the coefficient of variation Cv of X is small. When Cv reaches 2.0 the Markov chain model still shows an error of less than 4 percent while the equivalent rate model exhibits a 50 percent error that, unlike the Markov chain model, continues to increase with increase in Cv. Finally, it is shown that BW drops significantly with increase in Cv. suggesting that processor-memory transfers should use a fixed block size if memory conflict is to be minimized.