Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks
IEEE Transactions on Computers - The MIT Press scientific computation series
Performance of unbuffered shuffle-exchange networks
IEEE Transactions on Computers - The MIT Press scientific computation series
A connecting network with fault tolerance capabilities
IEEE Transactions on Computers - The MIT Press scientific computation series
The Load-Sharing Banyan Network
IEEE Transactions on Computers
Path hierarchies in interconnection networks
IBM Journal of Research and Development
The effect of operation scheduling on the performance of a data flow computer
IEEE Transactions on Computers
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
An analytical model for a class of processor-memory interconnection networks
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
Combining produce and consume operations in a pipelined shared memory multiprocessor
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Traffic studies of unbuffered Delta networks
IBM Journal of Research and Development
The Folded Hypercube ATM Switches
ICN '01 Proceedings of the First International Conference on Networking-Part 2
Performing BMMC Permutations in Two Passes through the Expanded Delta Network and MasPar MP-2
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Performance Analysis of Multistage Interconnection Networks using a Multicast Algorithm
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
The Stereo Correspondence Problem on a Ring-based Network
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Analysis of a multistage interconnection network using binary decision diagrams (BDD)
SRDS '96 Proceedings of the 15th Symposium on Reliable Distributed Systems
Performance Analysis of a Multicast Switch Based on Multistage Interconnection Networks
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Circular window control schemes in fast packet switches
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
Distributed, Dynamic Control of Circuit-Switched Banyan Networks
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Performance Analysis of Optical Multistage Interconnection Networks with Limited Crosstalk
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 15 - Volume 16
A Comparative Performance Study of an Interconnection Cached Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations
IEEE Transactions on Computers
Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
Comments on "Interference Analysis of Shuffle/Exchange Networks"
IEEE Transactions on Computers
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
PUMPS Architecture for Pattern Analysis and Image Database Management
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Routing Schemes for the Augmented Data Manipulator Network in an MIMD System
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers
IEEE Transactions on Parallel and Distributed Systems
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Fast reconfiguration algorithms for time, space, and wavelength dilated optical Benes networks
International Journal of Parallel, Emergent and Distributed Systems
Journal of Discrete Algorithms
An interleaved array-processing architecture
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
Distributed scheduling of resources on interconnection networks
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
A New Dimension Analysis on Blocking Behavior in Banyan-Based Optical Switching Networks
IEICE - Transactions on Information and Systems
Architecture-aware LDPC code design for multiprocessor software defined radio systems
IEEE Transactions on Signal Processing
Reliability and path length analysis of irregular fault tolerant multistage interconnection network
ACM SIGARCH Computer Architecture News
A combinatorial approach to performance analysis of a shared-memory multiprocessor
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
Analysis of space-time tradeoffs in photonic switching networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
A Comparative Study of Distributed Resource Sharing on Multiprocessors
IEEE Transactions on Computers
Reliability analysis of multi-path multi-stage interconnection network
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata
Microelectronics Journal
Review: Performance estimation of banyan semi layer networks with drop resolution mechanism
Journal of Network and Computer Applications
Towards peta-bit photonic networks
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
Research: MS4 - a high performance output buffering ATM switch
Computer Communications
Circular window control schemes in fast packet switches
Computer Communications
Input queued switches for variable length packets: analysis for Poisson and self-similar traffic
Computer Communications
An analytical model for the performance of buffered multicast banyan networks
Computer Communications
On Different Models for Packet Flow in Multistage Interconnection Networks
Fundamenta Informaticae
| Hi-index | 15.05 |
A class of interconnection networks based on some existing permutation networks is described with applications to processor to memory communication in multiprocessing systems. These networks, termed delta networks, allow a direct link between any processor to any memory module. The delta networks and full crossbars are analyzed with respect to their effective bandwidth and cost. The analysis shows that delta networks have a far better performance per cost than crossbars in large multiprocessing systems.