Theory of Modeling and Simulation
Theory of Modeling and Simulation
Multitasking on FPGA Coprocessors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Chip-Based Reconfigurable Task Management
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
The role of virtualization in embedded systems
Proceedings of the 1st workshop on Isolation and integration in embedded systems
RDMS: A hardware task scheduling algorithm for Reconfigurable Computing
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Processor virtualization and split compilation for heterogeneous multicore embedded systems
Proceedings of the 47th Design Automation Conference
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
Secure virtualization within a multi-processor soft-core system-on-chip architecture
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
| Hi-index | 0.00 |
This work presents an approach for virtualization-driven mapping and switching of software tasks for embedded multi-processor System-on-Chips (MPSoCs). We exploit a dedicated Virtualization Middleware between an array of processors and independent software tasks. Thus, the usually strict and static processor-to-task binding is resolved. By introducing a dynamically reconfigurable interconnection network based on permutation networks inside this Virtualization Middleware, an easy mapping and scheduling of software task groups may be achieved. Emphasis is put on the scalability as well as on the generic structure of the proposed solution. Sharing processor resources among software tasks and the ability to realize load distribution between processors are built-in features. Neither the software tasks nor the processors employed have to be modified in order to be used with the proposed procedure. The approach is demonstrated by a state-of-the-art cryptographic computation example, where the process of eight parallel AES-128 encryptions and decryptions is dynamically mapped and (re-)scheduled on a parallel array of embedded soft-core processors.