Parallel Computations on Reconfigurable Meshes
IEEE Transactions on Computers
Sequencing run-time reconfigured hardware with software
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Run-time compaction of FPGA designs
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Run-Time Management of Dynamically Recongigurable Designs
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Incremental reconfiguration for pipelined applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Configuration Relocation and Defragmentation for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Run time reconfiguration of FPGA for scanning genomic databases
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Multithreading for Logic-Centric Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Partially Reconfigurable Cores for Xilinx Virtex
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2D defragmentation heuristics for hardware multitasking on reconfigurable devices
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Secure virtualization within a multi-processor soft-core system-on-chip architecture
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
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Modularity is a key aspect of system design, particularly in the era of system-on-chip. Field-programmable logic (FPL), particularly with the rapid increase in programmable gate counts, is a natural medium to host run-time modularity, that is, a dynamically-varying ensemble of circuit modules. Prior research has presumed the use of an external processor to manage such an ensemble. In this paper, we consider on-chip management, implemented in the FPL itself, based upon a one-dimensional allocation model. We demonstrate an algorithm for on-chip identification of free FPL resource for modules, and an approach to on-chip rearrangement of modules. The latter includes a proposal for a realistic augmentation to existing FPGA reconfiguration architectures. The work represents a key demonstration of how FPL can be used as a first-order computational resource, rather than just as a slave to the microprocessor.