Statecharts: A visual formalism for complex systems
Science of Computer Programming
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Applied operating system concepts
Applied operating system concepts
Run-time compaction of FPGA designs
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Router Modules Using Network Protocol Wrappers
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Chip-Based Reconfigurable Task Management
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Memory centric thread synchronization on platform FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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This paper concerns 'logic-centric' systems on chip, that is, systems in which the main computational focus is on logic circuitry -- specifically programmable logic circuitry here. In particular, processors have a subordinate role to the logic in such systems. The key idea pursued in the paper is the importation and adaptation of the concept of multithreading from the world of the processor into the world of programmable logic, as one element in a higher-level model of logic-centric computation. A general mechanism for implementing time slicing for multithreading, and for dealing with synchronization issues that arise, is presented. Then, an actual case study is described: the implementation of a multiversion IP router on the Xilinx Virtex-II Pro part, where multithreading was profitably introduced into a system design in order to minimize latency when handling packets at gigabit rates.