Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time compaction of FPGA designs
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Video communications using rapidly reconfigurable hardware
IEEE Transactions on Circuits and Systems for Video Technology
Multithreading for Logic-Centric Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Chip-Based Reconfigurable Task Management
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
New three-level resource management enhancing quality of offline hardware task placement on FPGA
International Journal of Reconfigurable Computing
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
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Partially reconfigurable FPGAs can be shared among multiple independent tasks. When partial reconfiguration is possible at runtime the FPGA controller can decide on-line were to place new tasks on the FPGA. Since on-line allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit noncontiguous resources available to service them. Rearranging a subset of the tasks executing on the FPGA often allows the next pending task to be processed sooner. In this paper we study the problem of placing and rearranging tasks that are supplied by input streams which have constant data rates. When such tasks are rearranged, the arriving input data have to be buffered while the execution is suspended. We describe and evaluate a genetic algorithm for identifying and scheduling feasible rearrangements when moving tasks are reloaded from off-chip and buffer size is limited.