Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Task Graph Scheduling Using Timed Automata
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
A Preliminary Evaluation of the Critical Path Method for Scheduling Tasks on Multiprocessor Systems
IEEE Transactions on Computers
A new strategy for multiprocessor scheduling of cyclic task graphs
International Journal of High Performance Computing and Networking
Intelligent merging online task placement algorithm for partial reconfigurable systems
Proceedings of the conference on Design, automation and test in Europe
A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
An ILP formulation for task mapping and scheduling on multi-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Hardware supported task scheduling on dynamically reconfigurable SoC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.