A bitstream reconfigurable FPGA implementation of the WSAT algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Chip-Based Reconfigurable Task Management
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Lava and JBits: From HDL to Bitstream in Seconds
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The case for reconfigurable hardware in wearable computing
Personal and Ubiquitous Computing
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Online Scheduling for Block-Partitioned Reconfigurable Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Low-Cost Realization of an Adaptable Protocol Processing Unit
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
Implementation of secure applications in self-reconfigurable systems
Microprocessors & Microsystems
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task.In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility.