A simulation tool for dynamically reconfigurable field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Configuration compression for FPGA-based embedded systems
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
The Garp Architecture and C Compiler
Computer
Designing and Debugging Custom Computing Applications
IEEE Design & Test
JRoute: A Run-Time Routing API for FPGA Hardware
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Sea Cucumber: A Synthesizing Compiler for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Partially Reconfigurable Cores for Xilinx Virtex
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Improved Functional Simulation of Dynamically Reconfigurable Logic
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Debugging Techniques for Dynamically Reconfigurable Hardware
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Design and Implementation of Viterbi Decoder Using FPGAs
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Lava and JBits: From HDL to Bitstream in Seconds
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient dynamic reconfiguration for multi-context embedded FPGA
Proceedings of the 21st annual symposium on Integrated circuits and system design
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Customized kernel execution on reconfigurable hardware for embedded applications
Microprocessors & Microsystems
A Performance Model for Run-Time Reconfigurable Hardware Accelerator
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems
Proceedings of the Conference on Design, Automation and Test in Europe
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
UML-Based design flow and partitioning methodology for dynamically reconfigurable computing systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Functionally verifying state saving and restoration in dynamically reconfigurable systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Simulation-based functional verification of dynamically reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
Clustering scheduling for hardware tasks in reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.