A compiler approach to fast hardware design space exploration in FPGA-based systems
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
RTL c-based methodology for designing and verifying a multi-threaded processor
Proceedings of the 39th annual Design Automation Conference
Compilation for FPGA-Based Reconfigurable Hardware
IEEE Design & Test
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.