Compilation for FPGA-Based Reconfigurable Hardware

Authors:
João M. P. Cardoso;Horácio C. Neto
Affiliations:
-;-
Venue:
IEEE Design & Test
Year:
2003

Citing 11
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Abstract

These techniques for compiling software programs into reconfigurable hardware offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this article uses intermediate graph representations to embody parallelism at various levels.