Modern VLSI design (2nd ed.): systems on silicon
Modern VLSI design (2nd ed.): systems on silicon
Resolving non-uniqueness in design feature histories
Proceedings of the fifth ACM symposium on Solid modeling and applications
An Algorithm for Subgraph Isomorphism
Journal of the ACM (JACM)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Comparison of Algorithms for Maximum Common Subgraph on Randomly Connected Graphs
Proceedings of the Joint IAPR International Workshop on Structural, Syntactic, and Statistical Pattern Recognition
Compilation for FPGA-Based Reconfigurable Hardware
IEEE Design & Test
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA-Based System Design
Design of reconfigurable processors
Design of reconfigurable processors
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Maximum edge matching for reconfigurable computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A high-level target-precise model for designing reconfigurable HW tasks
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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This paper proposes a novel common subgraph extraction algorithm which aims to minimize the total number of gates (reconfiguration area overhead) involved in implementing compute-intensive scientific and media applications using reconfigurable architectures. Motivation behind the proposed research is illustrated using an example from Biochemical Algorithms Library (BALL). The design of novel context adaptable architectures to implement common subgraphs is also proposed with an example from the video warping functions of the MPEG-4 standard. Three different models of mapping such architectures onto hybrid/pure FPGA systems are proposed. Estimates obtained by applying these techniques and architectures for various media and scientific functions are shown.