IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
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Several applications in the media and scientific domain are often based on algorithms that employ intense computation kernels, embedded in vast control flow graphs. Such algorithms in a given application class involve many kernels with correlations in computational structures at functional and sub-functional levels. The large amount of instruction level parallelism in such applications has been traditionally captured and processed by high-end General Purpose Processors (GPPs). Although GPPs offer the flexibility needed to support progressive algorithmic refinement, they rely on very complex hardware support (superscalar machines), which are difficult to design or rely on complex compilers (very long instruction word machines) to provide parallel execution. The generic nature of their architecture limits their ability to fully exploit potential parallel executions available in scientific applications. Reconfigurable processors have been making significant progress in the area of accelerating applications by offering spatial hardware parallelism, which enables them to achieve speeds close to Application Specific Integrated Circuits (ASIC). They also offer a programmable platform (like GPPs) to facilitate execution of a variety of algorithms through a reconfigurable logic and network fabric. However, current reconfigurable architectures suffer from the drawback of large reconfiguration times and inefficient use of gates. This dissertation addresses the problem of reducing reconfiguration cycles and gate consumption for the execution of core basic blocks of scientific and media applications, through the design of context-adaptable hardware architectures based on the identification of reusable data computation patterns in applications.