A high-level target-precise model for designing reconfigurable HW tasks

Authors:
Maik Boden;Steffen Rülke;Jürgen Becker
Affiliations:
Fraunhofer IIS, EAS Dresden, Dresden, Germany;Fraunhofer IIS, EAS Dresden, Dresden, Germany;University of Karlsruhe, ITIV, Karlsruhe, Germany
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

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Abstract

The increasing complexity of embedded digital HW/SW systems, rising chip development and fabrication costs, and a shortened time-to-market require system-level design methods and the use of reconfigurable architectures. Our design method concerns the modelling of a system and its HW tasks at a high abstraction level. Using design patterns and macros, our library-based approach provides a consistent flow from an executable specification to its implementation. These templates ease the efficient application of partially run-time reconfigurable architectures. A case study depicts the high-level modelling of a HW task and its implementation in detail.