A scheduling and resource allocation algorithm for hierarchical signal flow graphs
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Design assistance for CAD frameworks
EURO-DAC '92 Proceedings of the conference on European design automation
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
PSM: an object-oriented synthesis approach to multiprocessor system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
REMARC (abstract): reconfigurable multimedia array coprocessor
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A methodology for guided behavioral-level optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Space-time scheduling of instruction-level parallelism on a raw machine
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Maps: a compiler-managed memory system for raw machines
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Power efficient mediaprocessors: design space exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Using general-purpose programming languages for FPGA design
Proceedings of the 37th Annual Design Automation Conference
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Algorithms for High-Level Synthesis
IEEE Design & Test
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware
CONPAR 90/VAPP IV Proceedings of the Joint International Conference on Vector and Parallel Processing
Instruction-Level Parallelism for Reconfigurable Computing
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Data-Procedural Languages for FPL-based Machines
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
A run-time word-level reconfigurable coarse-grain functional unit for a VLIW processor
Proceedings of the 15th international symposium on System Synthesis
Compilation Approach for Coarse-Grained Reconfigurable Architectures
IEEE Design & Test
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Compilation Framework for a Dynamically Reconfigurable Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the tenth international symposium on Hardware/software codesign
An algorithm for mapping loops onto coarse-grained reconfigurable architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
The digital divide of computing
Proceedings of the 1st conference on Computing frontiers
Proceedings of the 1st conference on Computing frontiers
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 41st annual Design Automation Conference
From C Programs to the Configure-Execute Model
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Dynamic loop pipelining in data-driven architectures
Proceedings of the 2nd conference on Computing frontiers
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures
Journal of Parallel and Distributed Computing - Special issue on parallel bioinspired algorithms
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
Proceedings of the 2006 international symposium on Low power electronics and design
Integration, the VLSI Journal
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms
Microprocessors & Microsystems
Compiler assisted architectural exploration for coarse grained reconfigurable arrays
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The Journal of Supercomputing
A unified evaluation framework for coarse grained reconfigurable array architectures
Proceedings of the 4th international conference on Computing frontiers
Low power data processing system with self-reconfigurable architecture
Journal of Systems Architecture: the EUROMICRO Journal
The changing role of computer architecture education within CS curricula: invited presentation
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
RISPP: rotating instruction set processing platform
Proceedings of the 44th annual Design Automation Conference
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
Optimized mapping for enchancing the operation parallelism in coarse-grained reconfigurable arrays
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Embedded Computing Systems (TECS)
System architecture and implementation of MIMO sphere decoders on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Flexible system level design methodology targeting run-time reconfigurable FPGAs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Proceedings of the 45th annual Design Automation Conference
International Journal of Parallel, Emergent and Distributed Systems
Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor
Proceedings of the conference on Design, automation and test in Europe
Hybrid Pipeline Structure for Self-Organizing Learning Array
ISNN '07 Proceedings of the 4th international symposium on Neural Networks: Part II--Advances in Neural Networks
Using GPUs to improve multigrid solver performance on a cluster
International Journal of Computational Science and Engineering
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Resource aware mapping on coarse grained reconfigurable arrays
Microprocessors & Microsystems
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEICE - Transactions on Information and Systems
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Dynamic context management for low power coarse-grained reconfigurable architecture
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays
The Journal of Supercomputing
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor
Microprocessors & Microsystems
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Journal of Signal Processing Systems
An Application Development Framework for ARISE Reconfigurable Processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
BRICK: a multi-context expression grained reconfigurable architecture
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems
Proceedings of the 46th Annual Design Automation Conference
A minimum communication cost algorithm for dynamically reconfigurable computing system
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A parallel partitioning algorithm for parallel reconfigurable computing
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
EURASIP Journal on Embedded Systems
FleXilicon architecture and its VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-core signal processor for heterogeneous reconfigurable computing
SOC'09 Proceedings of the 11th international conference on System-on-chip
SOC'09 Proceedings of the 11th international conference on System-on-chip
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Modeling of interconnection networks in massively parallel processor architectures
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
MORA: a new coarse-grain reconfigurable array for high throughput multimedia processing
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Formalization of data flow computing and a coinductive approach to verifying flowware synthesis
Transactions on computational science I
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Journal of Signal Processing Systems
Dynamic context compression for low-power coarse-grained reconfigurable architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Proceedings of the Conference on Design, Automation and Test in Europe
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Maximum edge matching for reconfigurable computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A high-level target-precise model for designing reconfigurable HW tasks
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Binary acceleration using coarse-grained reconfigurable architecture
ACM SIGARCH Computer Architecture News
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power reconfiguration technique for coarse-grained reconfigurable architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Partitioning signal processing applications to different granularity reconfigurable logic
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Speedups from executing critical software segments to coarse-grain reconfigurable logic
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
The ARISE approach for extending embedded processors with arbitrary hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Improving performance of nested loops on reconfigurable array processors
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
A route system based on ant colony for coarse-grain reconfigurable architecture
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part II
Memory-centric communication architecture for reconfigurable computing
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Data-driven regular reconfigurable arrays: design space exploration and mapping
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Memory-Aware application mapping on coarse-grained reconfigurable arrays
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
EPIMap: using epimorphism to map applications on CGRAs
Proceedings of the 49th Annual Design Automation Conference
Symbolic modeling of a universal reconfigurable logic gate and its applications to circuit synthesis
Proceedings of the 2012 ACM Research in Applied Computation Symposium
ACM Transactions on Embedded Computing Systems (TECS)
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA
ACM Transactions on Architecture and Code Optimization (TACO)
Compiling control-intensive loops for CGRAs with state-based full predication
Proceedings of the Conference on Design, Automation and Test in Europe
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)
Proceedings of the 50th Annual Design Automation Conference
An on-chip network fabric supporting coarse-grained processor array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture customization of on-chip reconfigurable accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Evaluator-executor transformation for efficient pipelining of loops with conditionals
ACM Transactions on Architecture and Code Optimization (TACO)
Configurable range memory for effective data reuse on programmable accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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