A multi-core signal processor for heterogeneous reconfigurable computing

Authors:
D. Rossi;F. Campi;A. Deledda;C. Mucci;S. Pucillo;S. Whitty;R. Ernst;S. Chevobbe;S. Guyetant;M. Kühnle;M. Hübner;J. Becker;W. Putzke-Roeming
Affiliations:
ST Microelectronics, Agrate Brianza, Italy;ARCES, University of Bologna, Italy;ST Microelectronics, Agrate Brianza, Italy;ARCES, University of Bologna, Italy;ARCES, University of Bologna, Italy;Technische Universitat Braunschweig, Germany;Technische Universitat Braunschweig, Germany;CEA, Paris, France;CEA, Paris, France;ITIV, University of Karlsruhe, Germany;ITIV, University of Karlsruhe, Germany;ITIV, University of Karlsruhe, Germany;Thomson, Germany
Venue:
SOC'09 Proceedings of the 11th international conference on System-on-chip
Year:
2009

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Abstract

Reconfigurable computing holds the promise of delivering ASIC-like performance while preserving run-time flexibility of processors. In many application domains, the use of FPGAs is limited by area, power, and timing overheads. Coarse-Grained Reconfigurable Architectures offer higher computation density, but at the price of rather being domain specific. Programmability is also a major issue related to all of the described solutions. This paper describes a heterogeneous multi-core system-on-chip that exploits different flavours of reconfigurable computing, merged together in a high parallel on-chip and off-chip interconnect utilized for both data and configuration. The aim of this work is to deliver a single monolithic engine that capitalizes on the strong points of different reconfigurable fabrics, while providing a friendly programming interface. The user is ultimately able to manage a broad spectrum of different applications, exploiting the most efficient means of computation through utilization of each kernel, while retaining a software-oriented development environment as much as possible.