Rapid prototyping for wireless designs: the five-ones approach
Signal Processing - From signal processing theory to implementation
Functionally partitioned module-based programmable architecture for wireless base-band processing
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A consistent design methodology for wireless embedded systems
EURASIP Journal on Applied Signal Processing
The reconfigurable instruction cell array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor
Proceedings of the conference on Design, automation and test in Europe
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Journal of Signal Processing Systems
A multi-core signal processor for heterogeneous reconfigurable computing
SOC'09 Proceedings of the 11th international conference on System-on-chip
Journal of Signal Processing Systems
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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There is growing interest in the use of flexible digital signal processors for wireless systems, driven by the demands of time to market, cost pressure, the requirement for flexibility to cope with evolving standards, and rapidly increasing processing needs. Much of the discussion of these techniques involves terms like "efficient" or "cost-effective" without necessarily quantifying the terms. This article considers the various architectures applicable to a wideband CDMA node-B base station (ASIC, FPGA, traditional DSP, and two varieties of flexible DSP) and builds a quantitative total cost approach to evaluating them, including benchmarked performance data.