IEEE Transactions on Computers
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Augmenting a microprocessor with reconfigurable hardware
Augmenting a microprocessor with reconfigurable hardware
Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
System-level scheduling on instruction cell based reconfigurable systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automated dynamic throughput-constrained structural-level pipelining in streaming applications
Proceedings of the conference on Design, automation and test in Europe
BRICK: a multi-context expression grained reconfigurable architecture
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An ILP formulation for task mapping and scheduling on multi-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
The eISP low-power and tiny silicon footprint programmable video architecture
Journal of Real-Time Image Processing
Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
Journal of Signal Processing Systems
Rapid functional modelling and simulation of coarse grained reconfigurable array architectures
Journal of Systems Architecture: the EUROMICRO Journal
Code compression and decompression for coarse-grain reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical and effective domain-specific function unit design for CGRA
ICCSA'11 Proceedings of the 2011 international conference on Computational science and Its applications - Volume Part V
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a novel instruction cell-based re-configurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.