Imagine: Media Processing with Streams
IEEE Micro
Gprof: A call graph execution profiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
SIMPil: an OE integrated SIMD architecture for focal plane processing applications
MPPOI '96 Proceedings of the 3rd Conference on Massively Parallel Processing Using Optical Interconnections
Bilateral Filtering for Gray and Color Images
ICCV '98 Proceedings of the Sixth International Conference on Computer Vision
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems
Proceedings of the 32nd annual international symposium on Computer Architecture
Image Processing Chain for Digital Still Cameras Based on the SIMPil Architecture
ICPPW '05 Proceedings of the 2005 International Conference on Parallel Processing Workshops
HiveFlex-Video VSP1: Video Signal Processing Architecture for Video Coding and Post-Processing
ISM '06 Proceedings of the Eighth IEEE International Symposium on Multimedia
Configurable Multi-Processor Platforms for Next Generation Embedded Systems
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Adaptive Filtering for Color Image Sharpening and Denoising
ICIAPW '07 Proceedings of the 14th International Conference of Image Analysis and Processing - Workshops
The reconfigurable instruction cell array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive color filter array demosaicking based on constant hue and local properties of luminance
PSIVT'07 Proceedings of the 2nd Pacific Rim conference on Advances in image and video technology
Adaptive gamma processing of the video cameras for the expansion of the dynamic range
IEEE Transactions on Consumer Electronics
Linear demosaicing inspired by the human visual system
IEEE Transactions on Image Processing
High dynamic range image rendering with a retinex-based adaptive filter
IEEE Transactions on Image Processing
Enhanced Autofocus Algorithm Using Robust Focus Measure and Fuzzy Reasoning
IEEE Transactions on Circuits and Systems for Video Technology
CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
CMOS sensors are now more and more frequently integrated into popular consumer products. Images from these sensors thus need to be digitally processed for display purposes. To do so, CMOS sensors are associated with dedicated components that keep power consumption low. However, use of dedicated components limits hardware flexibility and prevents updating of image processing algorithms. This paper describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than 1 mm2 and 500 mW in TSMC 65 nm).