Design and Tool Flow of Multimedia MPSoC Platforms
Journal of Signal Processing Systems
The eISP low-power and tiny silicon footprint programmable video architecture
Journal of Real-Time Image Processing
| Hi-index | 0.00 |
As mobile displays proliferate across the world, and fixed video displays expand in size, consumers demand enhanced visual experiences while watching such displays. Competitive low-end to high-end markets are migrating to high-definition (HD) output displays driven by consumer demand. In order to generate high quality visual experiences on HD displays, video processing algorithms are becoming increasingly complex. Such complex HD algorithms require up to Tera-operations per second to generate acceptable HD video output. Silicon Hive's HiveFlex Video VSP1 processor services the needs all low to high end video displays by using a unique scaleable tiled architecture. The architecture of each tile is flexible, low-cost and low-power, resulting in an attractive IP solution targeting consumer Video Signal Processing (VSP) Systems on Chips (SoCs). The Video VSP1 tile presented here performs a variety of video coding algorithms commonly used in post processing of HD TV signals such as H264 decoding, de-interlacing, picture-rate up-conversion and others. H.264 or MPEG4-AVC is an advanced video coding standard targeting multiple markets such as broadcast and hand-held entertainment. In partnership with Silicon Hive, AllGo Embedded Systems has developed an H.264 decoder that is optimized for the HiveFlex VSP architecture. Multiple VSP tiles with configurable number of issue slots and SIMD architecture are used efficiently to implement H.264 video decoding at HD resolution.