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Distance transformations in digital images
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IEEE Transactions on Pattern Analysis and Machine Intelligence - Special Issue on Industrial Machine Vision and Computer Vision Technology:8MPart
Efficient Image Processing Algorithms on the Scan Line Array Processor
IEEE Transactions on Pattern Analysis and Machine Intelligence
The image processing handbook (2nd ed.)
The image processing handbook (2nd ed.)
IEEE Transactions on Computers
A Parallelizing Method for Implementing Image Processing Tasks on SIMD Linear Processor Arrays
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
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Proceedings of the 31st annual international symposium on Computer architecture
An Integrated Memory Array Processor for Embedded Image Recognition Systems
IEEE Transactions on Computers
A low-cost mixed-mode parallel processor architecture for embedded systems
Proceedings of the 21st annual international conference on Supercomputing
In-vehicle vision processors for driver assistance systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Proceedings of the conference on Design, automation and test in Europe
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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MUSP'10 Proceedings of the 10th WSEAS international conference on Multimedia systems & signal processing
Parallel image and video processing on distributed computer systems
WSEAS Transactions on Signal Processing
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Journal of Signal Processing Systems
Journal of Signal Processing Systems
The eISP low-power and tiny silicon footprint programmable video architecture
Journal of Real-Time Image Processing
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Embedded processors for video image recognition require to address both the cost (die size and power) versus real-time performance issue, and also to achieve high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear processor and memory array architecture that addresses these trading-off requirements. By using parallel and systolic algorithmic techniques, despite of its simple architecture IMAP achieves to exploit not only the straightforward per image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, under the use of an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, a latest IMAP processor, which integrates 128 of 100MHz 8 bit4-way VLIW PEs, 128 of 2KByte RAMs, and one 16 bit RISC control processor, into a single chip. The PE instruction set is enhanced for supporting 1DC codes. IMAP-CE is evaluated mainly by comparing its performance running 1DC codes with that of a 2.4GHz Intel P4 running optimized C codes. Based on the use of parallelizing techniques, benchmark results show a speedup of up to 20 for image filter kernels, and of 4 for a full image recognition application.