A VLIW vector media coprocessor with cascaded SIMD ALUs

Authors:
Takahisa Wada;Shunichi Ishiwata;Katsuyuki Kimura;Keiri Nakanishi;Masato Sumiyoshi;Takashi Miyamori;Masaki Nakagawa
Affiliations:
Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan;Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan;Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan;Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan;Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan;Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan;Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

Citing 4
Cited 0

Very Long Instruction Word architectures and the ELI-512

ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
The Vector-Thread Architecture

Proceedings of the 31st annual international symposium on Computer architecture
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Proceedings of the 32nd annual international symposium on Computer Architecture
SODA: A Low-power Architecture For Software Radio

Proceedings of the 33rd annual international symposium on Computer Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

High-definition video applications, such as digital TV and digital video cameras, require high processing performance for high-quality visual images in addition to a complex video CODEC. Pre-/postprocessing to improve video quality is becoming much more important because requirements for pre-/postprocessing vary among applications and processing algorithms have not been stabilized. Therefore, a new processor architecture that has a highly parallel datapath is needed. In this paper, we introduce a VLIW vector media coprocessor, "vector coprocessor (VCP)," that includes three asymmetric execution pipelines with cascaded SIMD ALUs. To improve performance efficiency, we reduce the area ratio of the control circuit while increasing the ratio of the arithmetic circuit. The total gate count of VCP is 1268 kgates and its maximum operating frequency is 300 MHz at 90-nm CMOS process. Some of the processing kernels in an adaptive prefilter that is applied to preprocessing for video encoding are evaluated. In the case of the edgeness and the sum of absolute differences, the performance is 183 giga operations per second. VCP offers enough performance for HD video processing and good cost-performance while all processing pipeline units operate effectively.