Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Dual-Edge Triggered Static Pulsed Flip-Flops
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems
Proceedings of the 32nd annual international symposium on Computer Architecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Process Variations and Process-Tolerant Design
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
Process variation-aware routing in NoC based multicores
Proceedings of the 48th Design Automation Conference
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
International Journal of Embedded and Real-Time Communication Systems
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Silicon-aware distributed switch architecture for on-chip networks
Journal of Systems Architecture: the EUROMICRO Journal
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We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC architectures using self-correcting links that automatically detect delay variations and compensate them. The correction is applied without increasing the switch-to-switch latency by substituting the output flip-flops of the sending switch with a self-correcting flip-flop followed by an adaptive voltage swing selector. Higher delay variations will result in a smaller slack in the switch-to-switch path, but the adaptive voltage swing selector could mitigate its impact on the NoC communication by increasing the voltage swing on the link, thus allowing a compensation of the delay variation. As a result, it is possible to tolerate delay variations at the cost of additional power consumption.