Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
FV encoding for low-power data I/O
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Proceedings of the conference on Design, automation and test in Europe
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Error-correction and crosstalk avoidance in DSM busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Review of Packet Switching Technologies for Future NoC
ICSENG '08 Proceedings of the 2008 19th International Conference on Systems Engineering
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching activity generation with automated BIST synthesis for performance testing of interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-Error-Tolerant Network-on-Chip Design Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
International Journal of Computer Applications in Technology
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Energy-efficient and reliable channels are provided for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. This self-calibrated low-power coding and voltage scaling technique increases reliability and reduces energy consumption simultaneously. The SCG coding is a joint bus and error correction coding scheme that provides a reliable mechanism for channels. In addition, it achieves a significant reduction in energy consumption via a joint triplication bus power model for crosstalk avoidance. Based on SCG coding scheme, the proposed self-calibrated voltage scaling technique adjusts voltage swing for energy reduction. Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. This approach makes the channels of OCINs tolerant of transient malfunctions and realizes energy efficiency.