Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A spatially-adaptive bus interface for low-switching communication (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances that are in the same order of magnitude as intrinsic capacitances as far as deep-submicron designs are concerned. This trend has been recognized in recent research work. In this work, we present a physical model that takes into account inter-wire capacitances. Subsequently we propose a novel encoding scheme based on this physical model and targeted for address buses. We demonstrate that our encoding method improves power consumption by up to 62.5% and thus is exceeding all current approaches including our own previous one. In addition, the hardware of the bus encoding/decoding interfaces is compact to implement. We have conducted extensive simulations using SOC applications like, for example, an MPEGII encoder to evaluate the advantages of our approach.