Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Using a Soft Core in a SoC Design: Experiences with picoJava
IEEE Design & Test
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Journal of Electronic Testing: Theory and Applications
Routing methodology for minimizing 1nterconnect energy dissipation
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
A Distributed Control Path Architecture for VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Bus energy consumption for multilevel signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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As the technology sizes of semiconductor devices continue to decrease, the effect of nanometer technologies on interconnects, such as crosstalk glitches and timing variations, become more significant. In this paper, we study the effect of nanometer technologies on energy dissipation in interconnects. We propose a new power estimation technique which considers DSM effects, resulting in significantly more accurate energy dissipation estimates than transition-count based methods for on-chip interconnects. We also introduce an energy minimization technique which attempts to minimize large voltage swings across the cross-coupling capacitances between interconnects. Even though the number of transitions may increase, our method yields a decrease in power consumption of up to 50%.