Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital systems engineering
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Estimation of power distribution in VLSI interconnects
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Accurate Energy and Thermal Model for Global Signal Buses
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Driving-scheme algorithms for intelligent energy-efficient high-voltage display drivers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An asynchronous ternary logic signaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A comprehensive analysis of energy consumption for voltage-mode multilevel signals on a nanometer-technology bus is presented. A transition-dependent model is used which allows simplified calculation of the energy consumption. The accuracy of the approach is demonstrated using circuit simulations of three different electrical models of the bus, namely, lumped-C, distributed-RC, and distributed-RLC networks. We also verify that bus energy consumption is independent of driver resistance, as predicted by the model. Finally, we present a comparative analysis of power consumption for multilevel and binary buses.