A comparison of scalable superscalar processors
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Encodings for high-performance for energy-efficient signaling
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Macro-modeling concepts for the chip electrical interface
Proceedings of the 39th annual Design Automation Conference
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
A Delay Model for Router Microarchitectures
IEEE Micro
Typing the ISA to cluster the processor
Future Generation Computer Systems - Parallel computing technologies (PaCT-2001)
Typing the ISA to Cluster the Processor
PaCT '01 Proceedings of the 6th International Conference on Parallel Computing Technologies
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Register Transformations with Multiple Clock Domains
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Repeater and current-sensing hybrid circuits for on-chip interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Exploring the VLSI Scalability of Stream Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Energy Efficient Signaling in Deep Submicron CMOS Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Token coherence: decoupling performance and correctness
Proceedings of the 30th annual international symposium on Computer architecture
Cg: a system for programming graphics hardware in a C-like language
ACM SIGGRAPH 2003 Papers
Energy-reliability trade-off for NoCs
Networks on chip
Clocking strategies for networks-on-chip
Networks on chip
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Mixed-clock issue queue design for energy aware, high-performance cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Merrimac: Supercomputing with Streams
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Scan Test Strategy for Asynchronous-Synchronous Interfaces
Journal of Electronic Testing: Theory and Applications
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified optimization framework for equalization filter synthesis
Proceedings of the 42nd annual Design Automation Conference
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
Proceedings of the 32nd annual international symposium on Computer Architecture
Jitter in Deep Sub-Micron Interconnect
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Driver pre-emphasis techniques for on-chip global buses
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Global signaling over lossy transmission lines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array
IEEE Design & Test
Coding schemes for chip-to-chip interconnect applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Streaming architectures and technology trends
SIGGRAPH '05 ACM SIGGRAPH 2005 Courses
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
The SegBus platform - architecture and communication mechanisms
Journal of Systems Architecture: the EUROMICRO Journal
Interconnect design considerations for large NUCA caches
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the conference on Design, automation and test in Europe
Executing irregular scientific applications on stream architectures
Proceedings of the 21st annual international conference on Supercomputing
Optimal selection of voltage regulator modules in a power delivery network
Proceedings of the 44th annual Design Automation Conference
Voltage-mode driver preemphasis technique for on-chip global buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Efficient and accurate eye diagram prediction for high speed signaling
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Analog Integrated Circuits and Signal Processing
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
IEEE Transactions on Circuits and Systems II: Express Briefs
Optimal design of the power-delivery network for multiple voltage-island system-on-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of driver preemphasis for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Local search: is brute-force avoidable?
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
License Plate Multi-DSP and Multi-FPGA Design and Realization in Highway Toll System
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
A 32-Gb/s on-chip bus with driver pre-emphasis signaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Development of a concept inventory test for signal and power integrity in electronic design
FIE'09 Proceedings of the 39th IEEE international conference on Frontiers in education conference
Bus energy consumption for multilevel signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
Journal of Electronic Testing: Theory and Applications
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
SRAM write-ability improvement with transient negative bit-line voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An asynchronous ternary logic signaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust 4-PAM signaling scheme for inter-chip links using coding in space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance, energy efficiency, and scalability with GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS driver-receiver pair for low-swing signaling for low energy on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 4th International Workshop on Network on Chip Architectures
Modelling and refinement of an on-chip communication architecture
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Mobile system considerations for SDRAM interface trends
Proceedings of the System Level Interconnect Prediction Workshop
Closed-Form bounds for interconnect-aware minimum-delay gate sizing
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Formal verification of synchronizers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Computers and Electrical Engineering
A fault tolerant approach to object oriented design and synthesis of embedded systems
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling
International Journal of Circuit Theory and Applications
Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
CACTI-IO: CACTI with off-chip power-area-timing models
Proceedings of the International Conference on Computer-Aided Design
International Journal of Embedded and Real-Time Communication Systems
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 10th FPGAworld Conference
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
A 33mW 12.5Gbps BiCMOS transmitter for high speed backplane applications
Microelectronics Journal
StarSync: An extendable standard-cell mesochronous synchronizer
Integration, the VLSI Journal
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