Communications of the ACM
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Digital systems engineering
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Low-latency asynchronous FIFO buffers
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A FIFO Ring Performance Experiment
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low latency self-timed flow-through FIFOs
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Journal of Signal Processing Systems
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A general method to make multi-clock system deterministic
Proceedings of the Conference on Design, Automation and Test in Europe
A low-area multi-link interconnect architecture for GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance, energy efficiency, and scalability with GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
A column parity based fault detection mechanism for FIFO buffers
Integration, the VLSI Journal
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A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18-µm CMOS full. custom design and a 0.18-µm CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580-MHz operation and 10.3-mW power dissipation while performing simultaneous FIFO READ and WRITE operations at 1.8 V.