Communications of the ACM
High performance communications in processor networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Implementation of a packet switching device as a delay-insensitive circuit
Proceedings of the 1993 symposium on Research on integrated systems
A family of routing and communication chips based on the Mosaic
Proceedings of the 1993 symposium on Research on integrated systems
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Introduction to VLSI Systems
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
High-Level Design of an Asynchronous Packet-Routing Chip
Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A parallel asynchronous implementation of a FIFO buffer is described and compared with the conventional alternative asynchronous implementation, Sutherland's micropipeline. The parallel design has the potential for significant reductions in propagation delay at the cost of insignificant increases in cycle-time (i.e. reduced throughput) and area. Although in certain applications, e.g. DSP, only high throughput may be important, in others, e.g. packet switching, throughout and propagation delay both matter. We consider the parallel design to be most useful as part of the interface circuitry required by devices that asynchronously exchange data in bursts over inter-chip communication wires and use a single acknowledge signal for each burst of data. In particular, a high-throughput multiple-burst signalling scheme is supported, in which a second burst of data is transmitted at the same time as the previous burst is acknowledged, effectively increasing the overall throughput.