High performance communications in processor networks

Authors:
C. R. Jesshope;P. R. Miller;J. T. Yantchev
Affiliations:
Dept. of Electronics and Computer Science, The University Southampton, England;Dept. of Electronics and Computer Science, The University Southampton, England;Dept. of Electronics and Computer Science, The University Southampton, England
Venue:
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Year:
1989

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Abstract

In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements - deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. This paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for 2-D array and toroidal networks. An implementation of this scheme on arrays of transputers is described. The scheme also serves as a basis for a very low latency routing strategy named the mad postman, a detailed implementation of which is described here as well.