Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
High performance communications in processor networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A 100 Mbps, LED through-wafer optoelectronic link for multicomputer interconnection networks
Journal of Parallel and Distributed Computing - Special issue on parallel computing with optical interconnects
High-Throughput, Low-Memory Applications on the Pica Architecture
IEEE Transactions on Parallel and Distributed Systems
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Enabling efficient high-performance communication in multicomputer interconnection networks
Enabling efficient high-performance communication in multicomputer interconnection networks
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
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Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communicate at significantly higher speeds while operating more efficiently to meet system size, weight, power, and energy requirements. As high-performance parallel computing architectures make their way into portable systems, compact, efficient, and error-tolerant computing and communication mechanisms will be required. This paper presents the High-Performance Efficient Router (HiPER), an efficient multidimensional router supporting high-throughput error-corrected communication channels. HiPER is a proof-of-concept vehicle for efficient implementations of routing, switching, and error control mechanisms. It combines mad postman (bit-pipelined) switching with dimension-order routing, producing a low-latency routing router that is less sensitive to message distance than a word parallel crossbar router. To maintain robust communication as link speeds increase and link power budgets decrease, HiPER employs flit-level hop-by-hop retransmission of erroneous flits, which provides built-in error control at the network level. Data presented on the implemented bit serial version of HiPER offer insight into future router designs with channel sizes between bit-serial and word-wide.