Digital systems engineering
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
IEEE Transactions on Parallel and Distributed Systems
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses
Proceedings of the 40th annual Design Automation Conference
A High-Speed Clockless Serial Link Transceiver
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A unified optimization framework for equalization filter synthesis
Proceedings of the 42nd annual Design Automation Conference
5Gbps serial link transmitter with pre-emphasis
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
New CMOS Class AB Transmitter for 10 Gb/s Serial Links
Analog Integrated Circuits and Signal Processing
A two-tone test method for continuous-time adaptive equalizers
Proceedings of the conference on Design, automation and test in Europe
An area-power efficient CMOS 4-PAM class AB current-mode pre-emphasis serial link transmitter
Analog Integrated Circuits and Signal Processing
An area-power efficient 4-PAM full-clock 10-Gb/s CMOS pre-emphasis serial link transmitter
Analog Integrated Circuits and Signal Processing
Architecture and design of a simultaneously bidirectional single-ended high speed chip-to-chip interface
A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links
Analog Integrated Circuits and Signal Processing
A 33mW 12.5Gbps BiCMOS transmitter for high speed backplane applications
Microelectronics Journal
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To operate a serial channel over copper wires at 4 Gb/s, we incorporate an 4-GHz FIR equalizing filter into a differential transmitter. The equalizer cancels the frequency-dependent attenuation caused by the skin-effect resistance of copper wire, giving a frequency response that is flat to within 5% over the band from 200 MHz to 2 GHz even over wires with 6 dB of high-frequency attenuation. All but the last stage of the transmitter operates at 400 MHz. The transmitter output stage uses a stable, 10-phase, 400-MHz clock to sequence an array of drivers that implement the FIR filter. We introduce the concept of digital-signal equalization, describe the system design, and circuit design of our equalizing transmitter, and present simulation results from a 4-Gb/s 0.5-mm CMOS transmitter.